3601 - LatticeECP3: Why do I need to indicate the Header credits while performing memory reads for the Lattice PCIe IP?

PCIe protocol classifies all transactions in two types:

- Posted

- Non-posted

In posted transactions, the Requester sends the TLP packet to the Completer, and the Completer will not send any completion TLP packet back to the Requester. So, Memory Write and Message transactions are posted transactions.

In non-posted transactions, the Requester sends the TLP packet to the Completer, and the Completer will send the completion TLP packets back to the Requester either with data or without data depending on the request sent to the Completer. So, Memory Read, Memory Read Lock, I/O Read, I/O Write, Configuration Read (type 0 and type 1) and Configuration Write (type 0 and type 1) are non-posted transactions.

IPexpress GUI:

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3601 - LatticeECP3: Why do I need to indicate the Header credits while performing memory reads for the Lattice PCIe IP?

3601 - LatticeECP3: Why do I need to indicate the Header credits while performing memory reads for the Lattice PCIe IP?

Related Articles

1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

7747 - Avant: DDR Memory Controller Revision and Migration Guide

2691 - PCI Express IP: Why does the TXPLL no longer lock in my PCIe design when I migrate to the latest version of the Lattice PCI Express IP?

7759 - DDR Memory Controller v2.6.0 - Driver API caused invalid training status

1296 - Do the Lattice PCIe DevKit endpoint reference designs support Write-Combining transactions?