7560 - LatticeECP3\ECP5: What is the PCIe Advanced Error Reporting header format of err_tlp_header[127:0]?
Description:
The 128-bit AER bus of err_tlp_header[127:0] Header Word 0 starts at [127:96]. The interpretation is as below:
[127:96] - Header Word 0 (Fmt, Type, TC, TD, EP, Attr, Length)
[95:64] - Header Word 1 (Requester ID, Tag, Last DW BE, First DW BE)
[63:32] - Header Word 2 (Higher Address[63:32])
[31:0] - Header Word 3 (Lower Address[31:0])
Related Articles
6978 - PCIe for ECP5: How to disable the Advanced Error Reporting (AER) of the ECP5 PCIe IP ?
Solution: Untick the box of "Use Advanced Error Reporting" in the PCIe IP GUI to disable the AER.
1301 - PCIe: What Transaction Layer Packets (TLPs) header format is used for 64-bit addressing?
PCIe supports both 32-bit and 64 bit addressing. For 32-bit addressing a 3-DW header is used, containing just 32-bits of address info. For 64-bit addressing, a 4-DW header is used, with the extra DW holding the additional 32-bits of addressing.
6919 - Nexus / PCIe: How to determine the total DW of TLP to be received by link[LINK]_rx_data_o?
Description: Referring to the TLP fields of the PCI-Express Base Specification (https://pcisig.com/specifications), the ‘Fmt’ will determine the desired format of TLP.
7189 - CertusPro-NX/PCI Express: What is the AHB slave interface Endianness completion format for PCIe x4?
Description: Bytes 8-11 here illustrate Memory TLP, which contains Address field. It could be other fields, depending on the TLP type. Bytes 12-15 here show the payload field for 3-DW header TLP. It could be a 4th-DW header field, or it does not ...
3601 - LatticeECP3: Why do I need to indicate the Header credits while performing memory reads for the Lattice PCIe IP?
PCIe protocol classifies all transactions in two types: - Posted - Non-posted In posted transactions, the Requester sends the TLP packet to the Completer, and the Completer will not send any completion TLP packet back to the Requester. So, Memory ...