6919 - Nexus / PCIe: How to determine the total DW of TLP to be received by link[LINK]_rx_data_o?

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• 6236 - PCIe for Nexus FPGAs: What is the total amount of PCIe interfaces in CertusPro-NX-100 with different lanes?

  The PCI Express Link Layer Quad for all CertusPro-NX devices has four PIPE interfaces that can be used in different number of links. This can provide the maximum flexibility, depending on the bandwidth of the application requirements. The PCIe link ...

• 6934 - PCIe for Nexus FPGA: How to write the Link Layer Configuration Space Registers on PCIe device?

  Solution: 1. Defining the usr_lmmi_offset_i [16:2] a. usr_lmmi_offset_i [16] == selects between Link Layer or PHY register access b. usr_lmmi_offset [15:2] == refer to FPGA-IPUG-02126 à word aligned offset of base + offset address 2. Write “1’b0” on ...

• 6609 - All Nexus/PCIe: What clock does "link[LINK]_perst_n_i" and "link[LINK]_rst_usr_n_ " synchronized with?

  In TLP interface, both perst_n and rst_usr_n are asynchronous from the user perspective. There are built-in synchronizers for these resets.

• 6250 - PCIe for Nexus FPGAs: In PCIe X4 IP Core, I have selected AHB_LITE as the Data Interface Type. What is the clock domain for this interface?

  clk_usr_o originates from the PCIe Core, bypassing the PCIe Soft IP. It serves as an output to an external pin. Additionally, there are two input clocks for the Soft IP: clk_usr_i at 250 MHz and clk_usr_div2_i at 125 MHz.

• 6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?

  Description: There are some parameters that cannot be configured using LMMI. Example, in these 2 parameters: a) Target Link Speed – this is possible. The LMMI write needs to happen before PHY out of reset b) Use TLP Interface – this is not possible ...