6609 - All Nexus/PCIe: What clock does "link[LINK]_perst_n_i" and "link[LINK]_rst_usr_n_ " synchronized with?

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• 6934 - PCIe for Nexus FPGA: How to write the Link Layer Configuration Space Registers on PCIe device?

  Solution: 1. Defining the usr_lmmi_offset_i [16:2] a. usr_lmmi_offset_i [16] == selects between Link Layer or PHY register access b. usr_lmmi_offset [15:2] == refer to FPGA-IPUG-02126 à word aligned offset of base + offset address 2. Write “1’b0” on ...

• 1792 - [LatticeECP3]: Can I connect both the "mem_rst_n" and "rst_n" signals in the Lattice DDR3 IP core together to a system reset to meet the JEDEC initialization requirement?

  The "rsn_n" signal resets both the DDR3 memory controller and the DDR3 memory devices while the "mem_rst_n" signal resets only the DDR3 memory devices. The JEDEC specification has two different cases of reset initialization. Power-up reset ...

• 6250 - PCIe for Nexus FPGAs: In PCIe X4 IP Core, I have selected AHB_LITE as the Data Interface Type. What is the clock domain for this interface?

  clk_usr_o originates from the PCIe Core, bypassing the PCIe Soft IP. It serves as an output to an external pin. Additionally, there are two input clocks for the Soft IP: clk_usr_i at 250 MHz and clk_usr_div2_i at 125 MHz.

• 6927 - PCIe for Nexus FPGAs: Using the Lattice CertusPro-NX PCIe x4 IP Core and the AXI4-Stream interface, what is the latency of read and write access through the APB interface across the Link Layer registers, Configuration Space Registers, and the Soft

  Here is the latency table of the read & write through the APB interface for CertusPro-NX:

• 7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?

  Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...