1792 - [LatticeECP3]: Can I connect both the "mem_rst_n" and "rst_n" signals in the Lattice
DDR3 IP core together to a system reset to meet the JEDEC initialization
requirement?
The "rsn_n" signal resets both the DDR3 memory controller and the DDR3 memory devices while the "mem_rst_n" signal resets only the DDR3 memory devices. The JEDEC specification has two different cases of reset initialization.
Power-up reset initialization:
- The memory reset needs to be asserted at least 200us with stable power. In this case, there is no need for the memory clock (CK) to be stable according to JEDEC. Since the DDR3 IP core does not provide a wait counter for this requirement, it is user's responsibility to ensure to meet the required reset duration.
- Reset assertion with stable power:
- Once the reset is asserted, according to JEDEC, it is required to remain below 0.2 * VDD for minimum 100ns. The Lattice DDR3 IP core supports this requirement. When you assert a reset pulse which is shorter than 100ns on mem_rst_n, the core will ensure it is asserted at least for 100ns.
With these conditions, the user can connect their system reset to both "rst_n" and "mem_rst_n" if the system reset duration is guaranteed longer than 200us after power becomes stable. If not, the user will need to keep the mem_rst_n signal asserted at least for 200us with stable power to follow the JEDEC memory power-on reset requirement.