2583 - DDR3 IP: Does the Lattice DDR3 IP core automatically perform the ZQ calibaration and Auto Refresh commands during or after the initialization?

During initialization
The DDR3 controller IP core performs both ZQ calibration long (ZQCL) and auto refresh commands during the DDR3 initialization process. It is a requirement defined by JEDEC DDR3 specification.
After initialization
After the initialization process is completed, the auto-refresh is still performed by the core at the interval configured with the tREFI parameter (Refresh interval time) and the number for the Auto-Refresh command burst (Auto Refresh Burst Count). Therefore, there is no need for you to do anything for the auto refresh.

As for the ZQ calibration, it is an optional process for you to perform the calibration on demand basis. The DDR3 IP core does not provide auto-periodic ZQ calibration once the initialization process is completed. However, the core provides two user commands, ZQ_LNG (ZQ calibration long) and ZQ_SHRT (ZQ calibration short), to calibrate the DDR3 memory as needed. Since this process may impact the throughput and it is not a requirement once the initialization is completed, the ZQ calibration control will only run if implemented by the user.

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2583 - DDR3 IP: Does the Lattice DDR3 IP core automatically perform the ZQ calibaration and Auto Refresh commands during or after the initialization?

2583 - DDR3 IP: Does the Lattice DDR3 IP core automatically perform the ZQ calibaration and Auto Refresh commands during or after the initialization?

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1723 - CPRI:&nbsp; Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation? &nbsp;

7759 - DDR Memory Controller v2.6.0 - Driver API caused invalid training status

1792 - [LatticeECP3]: Can&nbsp;I&nbsp;connect both&nbsp;the "mem_rst_n" and&nbsp;"rst_n" signals in the Lattice DDR3 IP core together&nbsp;to&nbsp;a&nbsp;system reset to meet the JEDEC&nbsp;initialization requirement?

6458 - CrossLink-NX: Why does I2C Master Core IP does not have documentation about I2C repeated start?

7747 - Avant: DDR Memory Controller Revision and Migration Guide

1723 - CPRI: Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation?

1792 - [LatticeECP3]: Can I connect both the "mem_rst_n" and "rst_n" signals in the Lattice DDR3 IP core together to a system reset to meet the JEDEC initialization requirement?