2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?

The "read_pulse_tap" port is an input signal to the DDR3 controller IP core. Each DQS group has its own 3-bit read_pulse_tap port to control the READ signal timing to the DQSBUF hardware module. The DDR3 IP core allows dynamic READ pulse timing changes. Therefore, the value can be changed dynamically and there is no need to reset the DDR3 IP core.

It is a good idea to change the read_pulse_tap value during the bus idling state instead of changing during DDR3 transactions to avoid any possible instantaneous data corruption. Please note that the read_pulse_tap signal is used as a static input in real applications although the IP core allows dynamic changes.

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2319 - [LatticeECP3]: Should I&nbsp;reset the Lattice DDR3 controller IP core after changing the&nbsp;"read_pulse_tap" signal?

2319 - [LatticeECP3]: Should I&nbsp;reset the Lattice DDR3 controller IP core after changing the&nbsp;"read_pulse_tap" signal?

Related Articles

7759 - DDR Memory Controller v2.6.0 - Driver API caused invalid training status

7747 - Avant: DDR Memory Controller Revision and Migration Guide

304 - DDR2:&nbsp; What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP core?

1792 - [LatticeECP3]: Can&nbsp;I&nbsp;connect both&nbsp;the "mem_rst_n" and&nbsp;"rst_n" signals in the Lattice DDR3 IP core together&nbsp;to&nbsp;a&nbsp;system reset to meet the JEDEC&nbsp;initialization requirement?

2294 - DDR3 PHY:&nbsp; What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?

2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?

2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?

304 - DDR2: What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP core?

1792 - [LatticeECP3]: Can I connect both the "mem_rst_n" and "rst_n" signals in the Lattice DDR3 IP core together to a system reset to meet the JEDEC initialization requirement?

2294 - DDR3 PHY: What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?