2294 - DDR3 PHY:  What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?

2294 - DDR3 PHY:  What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?

Both the data and address/command bus loading factors should be considered to answer the question.

The Lattice DDR3 controller and DDR3 PHY IP cores were validated to allow up to two-DDR3 data pin loading on the DQ, DQS and DM signals at the rate of 400MHz/800Mbps using a LatticeECP3 device. This means that the IP cores support up to two-rank (or two-chip selects) memory configurations. If your application is DDR3 DIMM(dual in-line memory module) based, you can use a single- or dual-rank DIMM module. Use of two separate single-rank modules is not recommended because the core's DDR3 ODT (on-die termination) control is optimized for a single DIMM configuration.

As for the address/command bus, you can drive up to 16-device loading on each address, command or control pad. 16-device loading is typical for a dual-rank DIMM. We recommend you use the 2T option when a dual-rank DIMM is used to provide the better setup and hold timing window. The 2T option is available when you generate a DDR3 core targeting a dual-rank DDR3 DIMM memory configuration.