304 - DDR2:  What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP core?

There are several possible reasons when the read data valid signal is not asserted at all during the read operation:

The read data valid signal is generated from the incoming DQS signal that is driven by a DDR2 memory device or memory module (except LatticeSC devices). Check if the DQS signal from the memory comes out and is connected to the DQS pad of the target device properly.
Missing or driving improper level of reference voltage (VREF) also causes problems on the data valid generation. Make sure the VREF1 pad of each FPGA bank is connected to the required reference voltage (0.9V for DDR2).
The PCB trace round trip delay must be compensated. If you use the Lattice DDR2 IP core, you can compensate the trace delay by providing a proper value on the read_pulse_tap input port. See the DDR1/DDR2 IP core user manual (ipug35.pdf) for compensating the PCB trace delay.

Note: If you generated a bitstream for a LatticeXP2 device using the old ispLEVER v7.0 SP2 software, the read data valid signal does not function properly. This was fixed in ispLEVER v7.1 or later version. If you are still using ispLEVER v7.0 SP2 with Lattice DDR2 IP core for LatticeXP2, please migrate to the latest ispLEVER or Lattice Diamond software.

Related Articles
2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?
The "read_pulse_tap" port is an input signal to the DDR3 controller IP core. Each DQS group has its own 3-bit read_pulse_tap port to control the READ signal timing to the DQSBUF hardware module. The DDR3 IP core allows dynamic READ pulse timing ...
7759 - DDR Memory Controller v2.6.0 - Driver API caused invalid training status
Description: The driver API for DDR Memory Controller v2.6.0, DDR_MC_DONE_BITS in ddr_mc_avant.h is incorrect and causing invalid training status. Wrong value: #define DDR_MC_DONE_BITS 0x0000007D Correct value: #define DDR_MC_DONE_BITS 0x0000007F ...
1723 - CPRI:  Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation?  
Lattice CPRI IP core (Common Public Radio Interface) itself provides the auto-negotiation function. There is a state machine that will automatically go through a searching state from one line rate to the next line rate, eventually it will find the ...
2294 - DDR3 PHY:  What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?
Both the data and address/command bus loading factors should be considered to answer the question. The Lattice DDR3 controller and DDR3 PHY IP cores were validated to allow up to two-DDR3 data pin loading on the DQ, DQS and DM signals at the rate of ...
2684 - DDR3 IP: Why do I have two top-level wrappers inside a DDR3 IP core package generated from IPexpress ? Which one should I use for my design?
The DDR3 IP core package includes two top-level wrapper files in two different places using the same name, ddr3_sdram_mem_top_wrapper.v or .vhd. One of them which is located in the directory "ddr_p_eval\<user_name>\impl" is used solely for the core ...

304 - DDR2:&nbsp; What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP core?

304 - DDR2:&nbsp; What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP core?

Related Articles

2319 - [LatticeECP3]: Should I&nbsp;reset the Lattice DDR3 controller IP core after changing the&nbsp;"read_pulse_tap" signal?

7759 - DDR Memory Controller v2.6.0 - Driver API caused invalid training status

1723 - CPRI:&nbsp; Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation? &nbsp;

2294 - DDR3 PHY:&nbsp; What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?

2684 - DDR3 IP: Why do I have two top-level wrappers inside a DDR3 IP core package generated from IPexpress ? Which one should I use for my design?

304 - DDR2: What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP core?

304 - DDR2: What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP core?

2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?

1723 - CPRI: Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation?

2294 - DDR3 PHY: What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?