6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?

Description:

To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details.

Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.

Figure 1: Configuration Space in PCIe Demo

Solution:

The formatting of this configuration space is described below.

 

Figure 2 PCIe Configuration space formatting in the demo

Referring to the PCIe IP User Guide, you can search for the base address within the document as demonstrated below. In this example, the base address for the PCIe Link Layer register space is indicated as 0xF000.

In the provided example, the offset address 0x04 refers to the Main Control 1 register.

These concepts and details apply to other PCIe base addresses as well. The RTL formatting and interpretation of the PCIe configuration space remain consistent across different base addresses within the PCIe user guide.

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