7192 - PCIe for Nexus FPGAs: Why do PCIe Configuration Space registers (i.e. Device ID, Vendor ID, etc) not persist after first enumeration?

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• 6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?

  Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.

• 6934 - PCIe for Nexus FPGA: How to write the Link Layer Configuration Space Registers on PCIe device?

  Solution: 1. Defining the usr_lmmi_offset_i [16:2] a. usr_lmmi_offset_i [16] == selects between Link Layer or PHY register access b. usr_lmmi_offset [15:2] == refer to FPGA-IPUG-02126 à word aligned offset of base + offset address 2. Write “1’b0” on ...

• 6927 - PCIe for Nexus FPGAs: Using the Lattice CertusPro-NX PCIe x4 IP Core and the AXI4-Stream interface, what is the latency of read and write access through the APB interface across the Link Layer registers, Configuration Space Registers, and the Soft

  Here is the latency table of the read & write through the APB interface for CertusPro-NX:

• 7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?

  Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...

• 6247 - PCIe for Nexus FPGAs: How to access PCIe peripherals using AHB-lite interface?

  Solution: DMA support must be enabled to access the PCIe endpoint through AHB-lite. The DMA (Direct Memory Access) support has an option to enable efficient data transfer when the device acts as an initiator or a master. For more information, refer ...