6978 - PCIe for ECP5: How to disable the Advanced Error Reporting (AER) of the ECP5 PCIe IP ?
Solution: Untick the box of "Use Advanced Error Reporting" in the PCIe IP GUI to disable the AER.
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7560 - LatticeECP3\ECP5: What is the PCIe Advanced Error Reporting header format of err_tlp_header[127:0]?
Description: The 128-bit AER bus of err_tlp_header[127:0] Header Word 0 starts at [127:96]. The interpretation is as below: [127:96] - Header Word 0 (Fmt, Type, TC, TD, EP, Attr, Length) [95:64] - Header Word 1 (Requester ID, Tag, Last DW BE, First ...
DisplayPort TX IP Version 2.1.0 does not support back-to-back video input without blanking interval
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3997 - [LatticeECP3] [PCIe IP]: Why does the Peripheral Component Interconnect (PCIe) Scatter Gather Direct Memory Access (SGDMA) demo design of LatticeECP3 Versa development kit throw an error when compiled with the standalone Synplify Pro?
Description: When the PCIe SGDMA demo design files are compiled in Synplify Pro, the Synplify Pro compiler considers the variable 'int' to be a System Verilog data type. Solution: This default setting of Synplify Pro is the reason for the error. This ...