6978 - PCIe for ECP5: How to disable the Advanced Error Reporting (AER) of the ECP5 PCIe IP ?
Solution: Untick the box of "Use Advanced Error Reporting" in the PCIe IP GUI to disable the AER.
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7560 - LatticeECP3\ECP5: What is the PCIe Advanced Error Reporting header format of err_tlp_header[127:0]?
Description: The 128-bit AER bus of err_tlp_header[127:0] Header Word 0 starts at [127:96]. The interpretation is as below: [127:96] - Header Word 0 (Fmt, Type, TC, TD, EP, Attr, Length) [95:64] - Header Word 1 (Requester ID, Tag, Last DW BE, First ...
3997 - [LatticeECP3] [PCIe IP]: Why does the Peripheral Component Interconnect (PCIe) Scatter Gather Direct Memory Access (SGDMA) demo design of LatticeECP3 Versa development kit throw an error when compiled with the standalone Synplify Pro?
Description: When the PCIe SGDMA demo design files are compiled in Synplify Pro, the Synplify Pro compiler considers the variable 'int' to be a System Verilog data type. Solution: This default setting of Synplify Pro is the reason for the error. This ...
1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?
Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...
1315 - PCIE IP: Why is a DRC error generated associated with the PCI Core signal/pin serrn (SERR#)?
SERR# is defined as an Open-Drain pin in the PCI Local Bus Specifications. In certain PCI applications, a PCI agent might be required to monitor the SERR# pin so that the agent can properly respond to the system error condition. When using one of the ...
6056 - ECP5/ECP5-5G: What speeds/data rates does the PCIe and PCIe-5G Endpoint IP support?
For ECP5 non-5G devices, PCIe Endpoint IP is to be used. This IP can only support up to Gen1 speed (2.5 Gbps data rate). For ECP5 5G devices, PCIe-5G Endpoint IP is to be used. This IP supports both Gen1 and Gen2 speed (5 Gbps data rate). After ...