3997 - [LatticeECP3] [PCIe IP]: Why does the Peripheral Component Interconnect (PCIe) Scatter Gather Direct Memory Access (SGDMA) demo design of LatticeECP3 Versa development kit throw an error when compiled with the standalone Synplify Pro?

Description: When the PCIe SGDMA demo design files are compiled in Synplify Pro, the Synplify Pro compiler considers the variable 'int' to be a System Verilog data type.

Solution: This default setting of Synplify Pro is the reason for the error. This default setting can be disabled by going to "Implementation Options" and unchecking the System Verilog option.

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3997 - [LatticeECP3] [PCIe IP]: Why does the Peripheral Component Interconnect (PCIe) Scatter Gather Direct Memory Access (SGDMA) demo design of LatticeECP3 Versa development kit throw an error when compiled with the standalone Synplify Pro?

3997 - [LatticeECP3] [PCIe IP]: Why does the Peripheral Component Interconnect (PCIe) Scatter Gather Direct Memory Access (SGDMA) demo design of LatticeECP3 Versa development kit throw an error when compiled with the standalone Synplify Pro?

Related Articles

2069 - LatticeECP3: What is the usage of WB_CTI_I signal in the Lattice PCI Express Scatter Gather DMA Demo design?

3646 - LatticeECP3: Where can I find documentation on the Windows drivers for PCIe Demos that are available for Lattice ECP3 Versa Development Kit?

3515 - PCIe of LatticeECP3: How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe (Peripheral Component Interconnect Express) Endpoint IP core?

3606 - LatticeECP3: Can we change the DEVSEL parameter to SLOW for the PCIe IP (Peripheral Component Interconnect Express) configuration space?

4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?