3646 - LatticeECP3: Where can I find documentation on the Windows drivers for PCIe Demos that are available for Lattice ECP3 Versa Development Kit?

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• 7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?

  Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...

• 3997 - [LatticeECP3] [PCIe IP]: Why does the Peripheral Component Interconnect (PCIe) Scatter Gather Direct Memory Access (SGDMA) demo design of LatticeECP3 Versa development kit throw an error when compiled with the standalone Synplify Pro?

  Description: When the PCIe SGDMA demo design files are compiled in Synplify Pro, the Synplify Pro compiler considers the variable 'int' to be a System Verilog data type. Solution: This default setting of Synplify Pro is the reason for the error. This ...

• 3515 - PCIe of LatticeECP3: How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe (Peripheral Component Interconnect Express) Endpoint IP core?

  The Peripheral Component Interconnect Express (PCIe) endpoint IP we have currently can support only up to 8 Message Interconnect Express (MSI) interrupts. This number of MSI interrupts available for the user can be checked in 'Multiple Message ...

• 4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

  Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other. The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 ...

• 1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

  Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...