7474 - All Nexus/PCIe: Does MSI pending bits are writable?

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• 7193 - PCIe for Nexus FPGAs: How to generate MSI Interrupts with PCIe x1 IP core?

  Solution: To successfully use the MSI Interrupt, the user needs to perform the workaround below. Uncheck the box for "Disable Legacy Interrupt" to enable the Legacy Interrupt. This is a controller code requirement. 'MSI pending bit' = 1 alone does ...

• 4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

  Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other. The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 ...

• PCIe DMA in Ring Buffer Operation mode unable to be stopped

  Title: PCIe DMA in Ring Buffer Operation Mode Cannot Be Stopped Unexpectedly Issue Description: When the PCIe DMA is configured to operate in Ring Buffer DMA mode for continuous transfers, the DMA operation cannot be stopped unexpectedly. If a device ...

• 3515 - PCIe of LatticeECP3: How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe (Peripheral Component Interconnect Express) Endpoint IP core?

  The Peripheral Component Interconnect Express (PCIe) endpoint IP we have currently can support only up to 8 Message Interconnect Express (MSI) interrupts. This number of MSI interrupts available for the user can be checked in 'Multiple Message ...

• 6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?

  Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo. Figure 1: ...