323 - What are the definitions of the BAR bits in PCI/PCIe application?

The bit definitions of BAR for memory base address register are:

Bit 0: reserved to 0 as memory space indicator.
Bit 2~1: 00 indicates 32-bit access space; while 11 indicates 64-bit access space.
Bit 3: 1 indicates that the memory is prefetchable, which means no side effect on read.
Bit 31~4: number of 0s in lowest bits are used to define memory bar size in 16-byte aligned address blocks, while highest bits should be all 1s during initialization.

Example 1:
For 32-bit wide 1KBytes non-prefetchable memory space, set the BAR to "0xFFFF_FC00".

Example 2:
For 32-bit wide 1MBytes prefetchable memory space, set the BAR to "0xFFF0_0008".

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323 - What are the definitions of the BAR bits in PCI/PCIe application?

323 - What are the definitions of the BAR bits in PCI/PCIe application?

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4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

7474 - All Nexus/PCIe: Does MSI pending bits are writable?

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