7022 - CertusPro-NX/MPCS: Does the MPCS IP GUI for CertusPro-NX has a way to validate if the FVCO (VCO frequency) is within the SerDes specification limit?

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• 6977 - [CertusPro-NX] Serdes/PCS: Why does the MPCS-8b10b IP fails in x8 lane simulation?

  Solution: The issue has been fixed in Radiant 2023.2 (MPCS IP version 1.4.2 or later).

• 7743 - How to implement Gigabit Ethernet in Certus-NX, CertusPro-NX, MachXO5-NX and CrossLink-NX FPGAs?

  Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...

• 6220 - CertusPro-NX: How to select the external SerDes reference clock (SD_EXT_x_REFCLKn) of MPCS?

  By using MPCS, the user does not need to specify the location of SD_EXT_x_REFCLKn using a constraint file. Example snippet of the implementation: DIFFCLKIO DIFFCLKIO_inst ( .CLKIN0_P (sd_ext_0_p_i), .CLKIN0_N (sd_ext_0_n_i), .CLKIN1_P (), .CLKIN1_N ...

• 6965 - Serdes/PCS: How to know if the two SerDes data rates can be generated with the same reference clock frequency?

  Description: From FPGA-TN-02245-1-1-CertusPro-NX-SerDes-PCS-User-Guide of the Appendix C. Calculating Parameters for SerDes PLL, it shows the available data rates with respect to the reference clock. However in any case that the desired data rate for ...

• DisplayPort TX IP Version 2.1.0 does not support back-to-back video input without blanking interval

  Description DisplayPort TX IP version 2.1.0 requires the video input to provide blanking interval between active horizontal video lines to ensure correct video data packing. Failure symptoms include no video image output or black screen, even though ...