6769 - MPCS IP: Why does the settings written to the PMA registers does not reflect to the actual signal?

• Related Articles

• 6977 - [CertusPro-NX] Serdes/PCS: Why does the MPCS-8b10b IP fails in x8 lane simulation?

  Solution: The issue has been fixed in Radiant 2023.2 (MPCS IP version 1.4.2 or later).

• 7022 - CertusPro-NX/MPCS: Does the MPCS IP GUI for CertusPro-NX has a way to validate if the FVCO (VCO frequency) is within the SerDes specification limit?

  Solution: The MPCS IP has an update that added the FVCO checker. It is available on Radiant 2023.2 or later. In case the user cannot upgrade to the said version, kindly file techsupport ticket to have an appropriate software patch. ...

• 6466 - MPCS IP: Can the equalization algorithm of the MPCS IP module be selected through the LMMI dynamically?

  This can be done dynamically using LMMI (Lattice Memory Mapped Interface). The user just has to write the register address value (‘d217) to the lmmi_offset_i (address/offset) to access that PMA register. The needed information are shown below: ...

• 6233 - SLVS-EC Receiver IP Core: How to Set Reference Clock Frequency of SLVS-EC Rx IP core?

  The “reference clock” corresponds to the IP port refclk_*. This port represents the differential clock of the internal MPCS PLL. It can be sourced from any clock signal capable of generating the MPCS clock frequency specified in the “MPCS Clock ...

• 3524 - Lattice ECP3: How can we access configuration registers of Lattice Tri-Speed Ethernet MAC (TSMAC) IP Core ?

  Configuration registers of Tri-Speed Ethernet MAC (TSMAC) IP Core can be accessed through Host Interface. Also, values for particular registers can be hard coded in the ts_mac_core.v file if you are not using any host interface module in your design.