1691 - LatticeECP3: Can LatticeECP3 support OC3/OC12/OC48 SONET/SDH framer or mapper applications?  

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• 1723 - CPRI:  Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation?  

  Lattice CPRI IP core (Common Public Radio Interface) itself provides the auto-negotiation function. There is a state machine that will automatically go through a searching state from one line rate to the next line rate, eventually it will find the ...

• 6114 - Crosslink NX : Are there any Reference Designs of DPHY for different applications as stated below? 1. Connecting Soft DPHY Rx module output to Soft DPHY Tx module input. 2. Image acquisition from a camera through Hard DPHY.

  Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...

• 2102 - LatticeECP3 : Does it support the 1.35V operation mode of the 1.35V DDR3 SDRAM?

  The DDR3L 1.35V devices support both the 1.5V and 1.35V operation modes. LatticeECP3 can support the DDR3L 1.35V devices when both are running in the 1.5V operation mode. This is because LatticeECP3 devices do not have 1.35V IO support. If you run a ...

• 1515 - LatticeECP3: Does Lattice have a demo package integrating the CPRI core with an Ethernet MAC, HDLC framer and processor core?

  Description: No. The current Lattice CPRI IP core demo has the C&M channels connection ports which can be connected to an HDLC framer and Ethernet MAC core. The demo has its own test pattern generator and checker, but it does not include the HDLC ...

• 1296 - Do the Lattice PCIe DevKit endpoint reference designs support Write-Combining transactions?

  Write-Combining allows the CPU to burst 64 byte MWr TLPs to a PCIe endpoint, but there are implications. PC CPUs have a memory caching mode known as Write-Combining (WC). Write Combining allows the memory manager of the CPU to buffer up writes ...