1690 - LatticeECP3: What are minimum and maximum voltage levels of SERDES inputs?

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• 2367 - LatticeECP3: How does the RX loss of signal detection circuitry in the LatticeECP3 SERDES/PCS react to a constant value or a drop in signal condition on the SERDES serial inputs?

  Description: The following sections describe how the LatticeECP3 SERDES/PCS RX loss of signal (LOS) detection circuitry works. Operation: The RX LOS detection circuitry detects the voltage swing on the HDINP/N pins as shown in the "Loss of Signal" ...

• 2888 - How to handle unused power supply inputs for SERDES channels for the LatticeECP2/M device?

  The SERDES design provides separate final stage Rx and Tx power nodes for each CML input and output buffer. These are identified as VCCIB and VCCOB for LatticeECP2/M. These allow the receiver input termination (50 Ohm, 75 Ohm, 2K Ohm) and transmitter ...

• 7337 - Avant-G/Avant-X: What is the max peak-to-peak voltage of differential refclk for SERDES?

  The max peak-to-peak input voltage of the differential reference clock for Avant-G and Avant-X is 1.15V, with a minimum = -0.3V.

• 1959 - [LatticeECP2/M] Can the SERDES input voltage threshold be modified to force the SERDES into a reset state?

  The SERDES input voltage threshold cannot be modified. But you can adjust the SERDES register RLOS_HSET(increase or reduce the threshold) which is described on page 72 of the LatticeECP2M SERDES/PCS Usage Guide, TN1124 If the SERDES input voltage is ...

• 1770 - LatticeECP3: Are there any special considerations to interface the LatticeECP3 SERDES to standard SFP transceiver modules?

  Referring to the Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA), the LatticeECP3 SERDES inputs and outputs are compatible with the specification. This allows for a very clean interface between the module and the fpga. The ...