In simulating designs for Lattice devices, this error may appear if there is no GSR instantiated in the testbench.
There is no planned fix for this simulation issue.
To work around this, please instantiate GSR on your testbench.
GSR is needed to simulate because all Lattice hard blocks and primitives are connected to GSR.
For VHDL:
Right below of the Architecture block, add the instantiation of GSR primitive as shown in the example below:
Architecture Testbench of TOP is
component GSR is
generic (SYNCMODE : string);
port( GSR_N : in std_logic; CLK : in std_logic);
end component;
begin
GSR_INST : GSR
generic map (SYNCMODE => "SYNC")
port map ( GSR_N => '1', CLK => OSC);
For Verilog:
GSR # (.SYNCMODE ("SYNC"))
GSR_INST (.GSR_N (1'b1), .CLK (OSC));