7337 - Avant-G/Avant-X: What is the max peak-to-peak voltage of differential refclk for SERDES?

• Related Articles

• 7350 - Avant-X 25G Ethernet: Why does Lattice Radiant Software show a critical warning when designing the 25G Ethernet IP on Avant-X FPGA with -2 and -1 performance grades?

  Description: The supported performance grade for Avant-X 25G Ethernet IP is -3 (fastest). Radiant's critical warning as below will appear when using -1 and -2 performance grade devices. This speed grade limitation applies only to Avant-X 25G Ethernet ...

• 7747 - Avant: DDR Memory Controller Revision and Migration Guide

  Description: This table is to provide guidelines to help customers select the appropriate Memory Controller IP for Avant devices in accordance to the supported Memory Controller IP version in Radiant Software Tools. User may choose to continue to use ...

• 1690 - LatticeECP3: What are minimum and maximum voltage levels of SERDES inputs?

  You may refer to Table 3-9 (Serial Input Data Specifications) of LatticeECP3 Family data sheet. The minimum and maximum voltage levels of LatticeECP3 SERDES inputs are defined as input levels (VRX-IN) in LatticeECP3 data sheet. The minimum input ...

• 6220 - CertusPro-NX: How to select the external SerDes reference clock (SD_EXT_x_REFCLKn) of MPCS?

  By using MPCS, the user does not need to specify the location of SD_EXT_x_REFCLKn using a constraint file. Example snippet of the implementation: DIFFCLKIO DIFFCLKIO_inst ( .CLKIN0_P (sd_ext_0_p_i), .CLKIN0_N (sd_ext_0_n_i), .CLKIN1_P (), .CLKIN1_N ...

• 1959 - [LatticeECP2/M] Can the SERDES input voltage threshold be modified to force the SERDES into a reset state?

  The SERDES input voltage threshold cannot be modified. But you can adjust the SERDES register RLOS_HSET(increase or reduce the threshold) which is described on page 72 of the LatticeECP2M SERDES/PCS Usage Guide, TN1124 If the SERDES input voltage is ...