6446 - CertusPro-NX SERDES: Should the unused channel/s on a SerDes Quad be powered?

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• 6447 - CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?

  CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.

• 2888 - How to handle unused power supply inputs for SERDES channels for the LatticeECP2/M device?

  The SERDES design provides separate final stage Rx and Tx power nodes for each CML input and output buffer. These are identified as VCCIB and VCCOB for LatticeECP2/M. These allow the receiver input termination (50 Ohm, 75 Ohm, 2K Ohm) and transmitter ...

• 7743 - How to implement Gigabit Ethernet in Certus-NX, CertusPro-NX, MachXO5-NX and CrossLink-NX FPGAs?

  Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...

• 1527 - LatticeECP3: Why is the SERDES Quad C powered by VCCIB instead of supplying 1.2v, or 1.5v with passive filtering?

  The SERDES Quad C of LatticeECP3 FPGA on the Video Protocol board is reserved for HDMI/DVI interface. The HDMI/DVI interface is using TMDS signaling which has a common mode voltage around 3V and a differential swing range of 400-600mV. In order for ...

• 6215 - Certus Pro-NX: Does Lattice CertusPro-NX supports PCIe via PIPE + Soft PCIELL?

  Solution: No, the CertusPro-NX only supports PCIe via PIPE + Hard PCIELL.