The SERDES design provides separate final stage Rx and Tx power nodes for each CML input and output buffer. These are identified as VCCIB and VCCOB for LatticeECP2/M. These allow the receiver input termination (50 Ohm, 75 Ohm, 2K Ohm) and transmitter output termination (50 Ohm, 75 Ohm, 5K Ohm) to be biased at different levels, independent of the core VCC voltage. The Rx termination (resistor connected to VCCIB) value can vary based on design requirements.
Lattice devices use several supplies for analog circuitry blocks of SERDES. All analog supply pins must be connected to a voltage supply regardless of whether the channel is used in the application. Unused channels can be powered off internally to conserve power. The analog supplies should be isolated on the PCB to deliver quiet, noise-free power supplies.
On unused channels, VCCTX, VCCRX, VCCP and VCCAUX33 should be powered up. VCCIB, VCCOB, HDINP/N, HDOUTP/N and REFCLKP/N should be left floating. Unused channel outputs are tristated, with approximately 10K Ohm internal resistor connecting between the differential output pair.
VCCAUX33 supplies power to termination resistors. It is recommended to have the PI filter like the other power supplies. VCCAUX33 noise will directly be coupled to high-speed I/O, HDIN/HDOUT. If VCCAUX (FPGA core power supply) is very clean, it can be connected to VCCAUX33.
For more details, refer to
TN1114, Electrical Recommendations for Lattice SERDES
http://www.latticesemi.com/view_document?document_id=20815
and TN1124, LatticeECP2/M SERDES/PCS Usage Guide