1720 - LatticeECP3: If I am not using one of the SERDES/PCS quads of my device, are there any special considerations as far as layout is concerned? If I don't want to use a quad of SERDES/PCS, what should I do with SERDES/PCS power and signal pins?

If you are not using SERDES/PCS, you need to do the following steps: 1. Connect power: VCCA and ground VSSA; 2. Let other power domains (VCCIB and VCCOB) floating; 3. Let the other signal pins such as ;HDINP/N, HDOUTP/N and REF-CLKP/N floating. all the unused channel outputs are tri-stated with approximately 10 KOhm internal resistor connecting between the differential output pair. You don't need to instantiate SERDES in the design at all. The whole SerDes is in power down mode without instantiation. User can also refer to TN1189 - Hardware Checklist, under section- LatticeECP3 SERDES/PCS Power Supplies.

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1720 - LatticeECP3: If I am not using one of the SERDES/PCS quads of my device, are there any special considerations as far as layout is concerned? If I don't want to use a quad of SERDES/PCS, what should I do with SERDES/PCS power and signal pins?

1720 - LatticeECP3: If I am not using one of the SERDES/PCS quads of my device, are there any special considerations as far as layout is concerned? If I don't want to use a quad of SERDES/PCS, what should I do with SERDES/PCS power and signal pins?

Related Articles

1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?

833 - Lattice Diamond: ECP2M: PCS: How can I control the location of an LatticeECP2M PCS block?

990 - Are there any pins that can't be used when the SERDES is being used?

1181 - Which clock do I use to sample the lsm_status*/ffs_ls_sync_status* signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?

1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

1181 - Which clock do I use to sample the lsm_status/ffs_ls_sync_status signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?