525 - Where is LatticeECP2/M Serdes Reset RTL code ?

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• 1959 - [LatticeECP2/M] Can the SERDES input voltage threshold be modified to force the SERDES into a reset state?

  The SERDES input voltage threshold cannot be modified. But you can adjust the SERDES register RLOS_HSET(increase or reduce the threshold) which is described on page 72 of the LatticeECP2M SERDES/PCS Usage Guide, TN1124 If the SERDES input voltage is ...

• 354 - Is there a Verilog code example available to illustrate how to use Comma boundaries For SERDES/PCS based devices to correct for 16/20 byte shifting in FPGA Interface RX DATA?

  For more background on 16/20 bit mode byte shifting, please refer to FAQ 355. The principles of byte shifting in 16/20-bit mode apply to the LatticeSC , LatticeECP3 and LatticeECP2M PCS blocks in 16/20 bit data mode. The following Verilog general ...

• 1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?

  The response applies to the LatticeECP2M/LatticeECP3/LatticeSC/M PCS/SERDES QUADS used in 10-bit RAW SERDES only mode. The assumption is that you are coding your own RTL 8b10b decoder in the fabric. Based on the definition of 8b10b codes , DATA=0x00 ...

• 2888 - How to handle unused power supply inputs for SERDES channels for the LatticeECP2/M device?

  The SERDES design provides separate final stage Rx and Tx power nodes for each CML input and output buffer. These are identified as VCCIB and VCCOB for LatticeECP2/M. These allow the receiver input termination (50 Ohm, 75 Ohm, 2K Ohm) and transmitter ...

• 2722 - SERDES/ECP3:Why do I receive data errors when I configure the LatticeECP3 SERDES/PCS in TX-to-RX Serial Loopback Mode?

  The TX-to-RX Serial Loopback Mode is supported in the LatticeECP3 device (see "Control Setup" and "TX-to-RX Serial Loopback Mode" sections of FPGA-TN-02190). In this loopback test mode, the TX output serial data is looped back into the RX SERDES CDR. ...