357 - Is is OK to terminate VCCIB/VCCOB (VDDIB/VDDOB) to power on unused SERDES channels of all Lattice SERDES/PCS based devices (LatticeECP2M / LatticeECP3 / LatticeSC/M)?
As per Lattice Technical Note TN1144, VCCIB and VCCOB are only used to supply input/output termination voltage to match the tranmission lines.
By default, if a channel is unused during the IPexpress PCS generation phase, the autoconfig file (.txt) will power down this channel. As a result, whether you terminate VCCIB/OB of the unused channels or leave them floating makes no difference.
Another situation is where you enable a channel in IPexpress and terminate VCCIB/VCCOB to power. If you later decide not to use the channel in hardware, then terminating VCCIB/VCCOB also has a minimal effect due to the lack of activity on that channel.
Related Articles
2888 - How to handle unused power supply inputs for SERDES channels for the LatticeECP2/M device?
The SERDES design provides separate final stage Rx and Tx power nodes for each CML input and output buffer. These are identified as VCCIB and VCCOB for LatticeECP2/M. These allow the receiver input termination (50 Ohm, 75 Ohm, 2K Ohm) and transmitter ...
1720 - LatticeECP3: If I am not using one of the SERDES/PCS quads of my device, are there any special considerations as far as layout is concerned?
If I don't want to use a quad of SERDES/PCS, what should I do with SERDES/PCS power and signal pins?
If you are not using SERDES/PCS, you need to do the following steps: 1. Connect power: VCCA and ground VSSA; 2. Let other power domains (VCCIB and VCCOB) floating; 3. Let the other signal pins such as ;HDINP/N, HDOUTP/N and REF-CLKP/N floating. all ...
344 - For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?
The answer depends both on device family and data rate: In the case of the LatticeSC device, the user can only use the CTC in the SGMII/GbE PCS IP. In the case of the LatticeECP2M and LatticeECP3 devices, the use of the hard PCS CTC depends on the ...
1181 - Which clock do I use to sample the lsm_status*/ffs_ls_sync_status* signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?
In the case of LatticeECP2M/LatticeECP3/LatticeSC/M SERDES/PCS QUADs, logic in the Link State Machine block generates the lsm_status*/ffs_ls_sync_status* signal. This logic is synchronous to the RX recovered clock. A single stage sync flop is OK to ...
356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?
You can use the word_align_en_[0-3]/ffc_enable_cgalign_ch[0-3] either in an 8b10b based or 10-bit SERDES only based mode. The simulation waveforms below shows how a low pulse on the word_align_en_0 (LatticeSC/LatticeECP3 signal that has same function ...