6447 - CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?

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• 6927 - PCIe for Nexus FPGAs: Using the Lattice CertusPro-NX PCIe x4 IP Core and the AXI4-Stream interface, what is the latency of read and write access through the APB interface across the Link Layer registers, Configuration Space Registers, and the Soft

  Here is the latency table of the read & write through the APB interface for CertusPro-NX:

• 6215 - Certus Pro-NX: Does Lattice CertusPro-NX supports PCIe via PIPE + Soft PCIELL?

  Solution: No, the CertusPro-NX only supports PCIe via PIPE + Hard PCIELL.

• 6236 - PCIe for Nexus FPGAs: What is the total amount of PCIe interfaces in CertusPro-NX-100 with different lanes?

  The PCI Express Link Layer Quad for all CertusPro-NX devices has four PIPE interfaces that can be used in different number of links. This can provide the maximum flexibility, depending on the bandwidth of the application requirements. The PCIe link ...

• 1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

  Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...

• 7158 - CertusPro-NX/PCI Express: Why does PCIe Gen3x1 and Gen3x4 simulation takes longer time to link-up?

  Solution: The RTL fix will be release on the new IP version (pciex4 ver. 2.40). Gen 3x1 (before fix) Gen 3x1 (after fix) Gen3x4 (before fix) Gen3x4 (after fix) pl_link_up 150us 218us 39us 39us dl_link_up 634us 253us 76us 76us