81 - How long does it take for the SerDes TX PLL to lock?

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• 2722 - SERDES/ECP3:Why do I receive data errors when I configure the LatticeECP3 SERDES/PCS in TX-to-RX Serial Loopback Mode?

  The TX-to-RX Serial Loopback Mode is supported in the LatticeECP3 device (see "Control Setup" and "TX-to-RX Serial Loopback Mode" sections of FPGA-TN-02190). In this loopback test mode, the TX output serial data is looped back into the RX SERDES CDR. ...

• 1947 - PCIe of LatticeECP3: How should 'tx_req' port should be implemented for better Tx throughput?

  For better Tx throughput, tx_req from user logic should be implemented such that gaps in tx_rdy are minimized. The Lattice PCIe IP core arbitrates among user (tx_req) and internal requests to assert tx_rdy to enable packet transmission through the ...

• 6924 - SerDes/PCS for ECP5/ECP5-5G: Why is TX-to-RX Serial Loopback not available in SerDes/PCS?

  The loopback mode is not a static setting, but rather is dynamically controlled through the SCI Interface using the SerDes Control Register 6 (CH_15) > lb_ctl[3:0]. Please refer to Appendix A. Configuration Registers > Per Channel SerDes Control ...

• 6979 - PCIe for Nexus FPGAs: Does the vc_tx_valid_i can be delayed (insert 3 clock cycles) during long external memory read since the FPGA lose the access for some clocks?

  Description: The vc_tx_valid_i should not be delayed or do insertion of the 3 clock cycles gap within packets as it affects the validity of the data thus it is forbidden to insert such delay. This cannot be use as a workaround for the long external ...

• 2245 - Lattice ECP3: Is it OK to loop XAUI data from the RX XGMII to TX XGMII if the IPG is always between 5 and 8 bytes long?

  Description:The IEEE 802.3ae Specification explains that it is possible for a 12 bytes IPG (Inter Packet Gap) to shrink to 5 bytes by the time it reaches the RX XGMII interface. This is due to many factors, including clock rate compensation. ...