5541 - LatticeECP5: Can the Clock Tolerance Compensation (CTC) can be modified in PCS IP?

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• 1991 - SGMII and Gb Ethernet PCS IP Core: How many idle ordered sets will the IP's Clock Tolerance Compensation logic insert or delete during an inter-packet gap period?

  The Clock Tolerance Compensation (CTC) logic in the SGMII and Gb Ethernet PCS IP Core performs both idle ordered set insertion when the CTC FIFO low watemark is reached and idle ordered set deletion when the CTC FIFO high watemark is reached. CTC ...

• 1692 - LatticeECP3: Can I use the clock tolerance compensation (CTC) function of LatticeECP3 family SERDES/PCS in 10BSER mode?

  For LatticeECP3 family, SERDES/PCS in 10BSER mode provides users the function of pure serialization and deserialization without the function of 8B10B encoder/decoder. You may have your own encoder/decoder. Therefore the CTC function is disabled in ...

• 4746 - LatticeECP3: How to check if the design uses the Clock Tolerance Circuit (CTC) inside the SerDes hard Physical Coding Sub-layer (PCS)?

  The PCS has an option in GUI to enable or disable the CTC block while generating the PCS IP through IP Express in Lattice Diamond. If the CTC block has been enabled in GUI, the design will use it.

• 344 - For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?

  The answer depends both on device family and data rate: In the case of the LatticeSC device, the user can only use the CTC in the SGMII/GbE PCS IP. In the case of the LatticeECP2M and LatticeECP3 devices, the use of the hard PCS CTC depends on the ...

• 2022 - Do Lattice XAUI PCS solutions only allow Ethernet frame sizes between 64 and 1518 bytes as specified in IEEE 802.3ae?

  There is no limitation on the Ethernet frame size as far as the Lattice XAUI PCS cores (LatticeSC flexiPCS Core and XAUI PCS IP Core for LatticeECP2M) are concerned. The XAUI PCS cores will allow transmission and reception of any frame size, ...