4746 - LatticeECP3: How to check if the design uses the Clock Tolerance Circuit (CTC) inside the SerDes hard Physical Coding Sub-layer (PCS)?

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• 1692 - LatticeECP3: Can I use the clock tolerance compensation (CTC) function of LatticeECP3 family SERDES/PCS in 10BSER mode?

  For LatticeECP3 family, SERDES/PCS in 10BSER mode provides users the function of pure serialization and deserialization without the function of 8B10B encoder/decoder. You may have your own encoder/decoder. Therefore the CTC function is disabled in ...

• 344 - For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?

  The answer depends both on device family and data rate: In the case of the LatticeSC device, the user can only use the CTC in the SGMII/GbE PCS IP. In the case of the LatticeECP2M and LatticeECP3 devices, the use of the hard PCS CTC depends on the ...

• 1873 - [LatticeECP3] Common Public Radio Interface - IP Core: Is the FIFO bridge in the PCS (Physical Coding Sub-layer) used in the low latency CPRI (Common Public Radio Interface) IP (Intellectual Property) core?

  LatticeECP3 supports CPRI (Common Public Radio Interface) low latency mode operation and the FIFO bridge in the SERDES/PCS is bypassed. The conditions are that the operation runs at full synchronous mode and data is handed off from SerDes/PCS to FPGA ...

• 5541 - LatticeECP5: Can the Clock Tolerance Compensation (CTC) can be modified in PCS IP?

  Description: The PCS IP fixed the CTC FIFO setting depending on the Protocol used. Customer can access to modify the code for it is not encrypted. Lattice strongly recommended customers not to modify the CTC as it is set to work as-is and modifying ...

• 1693 - LatticeECP3: When I do system debug with LatticeECP3 device, how can I generate a bitstream file to perform equalization series loopback without modifying my core design or re-generating SERDES/PCS module from IPExpress?

  For LatticeECP3 device, we provide equalization series loopback for system debug. The equalization series loopback means that the data from high speed input pins (HDINP/N) serially loopback to high speed output pins (HDOUTP/N) via equalization ...