1873 - [LatticeECP3] Common Public Radio Interface - IP Core: Is the FIFO bridge in the PCS (Physical Coding Sub-layer) used in the low latency CPRI (Common Public Radio Interface) IP (Intellectual Property) core?

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• 1723 - CPRI:  Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation?  

  Lattice CPRI IP core (Common Public Radio Interface) itself provides the auto-negotiation function. There is a state machine that will automatically go through a searching state from one line rate to the next line rate, eventually it will find the ...

• 1748 - Common Public Radio Interface - IP Core: Do I need to use a clock cleaner when using CPRI IP core (Common Public Radio Interface) with Lattice SERDES based FPGA?

  Lattice CPRI IP core (Common Public Radio Interface) supports LatticeECP2/M, LatticeECP3 and LatticeSC. When using the CPRI IP core in REC(Radio Equipment Control,master) mode, it's not necessary to use a clock cleaner since the system provides the ...

• 4746 - LatticeECP3: How to check if the design uses the Clock Tolerance Circuit (CTC) inside the SerDes hard Physical Coding Sub-layer (PCS)?

  The PCS has an option in GUI to enable or disable the CTC block while generating the PCS IP through IP Express in Lattice Diamond. If the CTC block has been enabled in GUI, the design will use it.

• 6927 - PCIe for Nexus FPGAs: Using the Lattice CertusPro-NX PCIe x4 IP Core and the AXI4-Stream interface, what is the latency of read and write access through the APB interface across the Link Layer registers, Configuration Space Registers, and the Soft

  Here is the latency table of the read & write through the APB interface for CertusPro-NX:

• 3843 - Are Lattice IP (Intellectual Property) reset signals connected to the GSR (Global Set/Reset) modules by default?

  The IP (Intellectual Property) reset signals of the Lattice IP cores are not connected to the GSR components by default. Hence, the users can connect their end design reset signals to the GSR component.