1855 - LatticeECP3: What is the recommended cable length for a CAT-6 cable that can be used with SERDES (Serializer/De-Serializer) transmit and receive data at a maximum speed of 3.125Gbps?

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• 351 - How do the VCCIB pins on the LatticeECP3 need to be connected if the SERDES receive inputs (HDIN) are not being used?

  If the SERDES receive input (HDIN) signals are not being used, you have the following options for connecting VCCIB: The LatticeECP3 SERDES input block can be powered down. When the SERDES input logic is not powered it is not necessary to connect the ...

• 7206 - PCIe for Nexus FPGAs: What is the size of the Transmit Buffer and Receive Buffer in PCIe X1 IP Core and PCIe X4 IP Core?

  The Transmit Buffer and Receive Buffer size is 2 kByte each. These RAM buffer sizes are fixed because it is a Core internal RAM, so the negotiated Maximum Payload Size (MPS) size will determine how many TLPs can be stored. For instance, in the ...

• 1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

  Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...

• 2533 - LatticeECP2M/ECP3: How can I access the full rate recovered clock to sample the receive data in a Lattice X1 Native PCIe IP targeting either LatticeECP2M or LatticeECP3 devices?

  Description: The X1 Native PCI Express IP uses the embedded Clock Tolerance Compensation FIFO in the LatticeECP2M/ECP3 SERDES. The receive data coming out of the FIFO is synchronous to the tx_full_clk. This clock should be used if you need to sample ...

• 2722 - SERDES/ECP3:Why do I receive data errors when I configure the LatticeECP3 SERDES/PCS in TX-to-RX Serial Loopback Mode?

  The TX-to-RX Serial Loopback Mode is supported in the LatticeECP3 device (see "Control Setup" and "TX-to-RX Serial Loopback Mode" sections of FPGA-TN-02190). In this loopback test mode, the TX output serial data is looped back into the RX SERDES CDR. ...