266 - What is the meaning of "ff_rxiclk_ch0" and "ff_ebrd_clk_0" and how to connect them in HD-SDI mode?
A1 : The clock "ff_ebrd_clk_0" is the read clock of the Elastic Buffer in PCS. The clock "ff_rxiclk_ch0" is the read clock of the Down Sample FIFO in PCS.
A2 : In HD-SDI mode, the CTC is bypassed, so "ff_ebrd_clk_0" could be connected to '0'; the "ff_rxdata_ch0" is a 20-bit-width signal and the data written into the Down Sample FIFO is a 10-bit-width signal, so the "ff_rxhalfclk_ch0" could be connected to "ff_rxiclk_ch0".
Related Articles
2321 - ECP3: In LatticeECP3, can I use the receiver for 2.97Gbps HDMI and the transmitter for 3G SDI(or HD_SDI) in the same channel?
It is possible. In the IPexpress GUI, select SDI as the protocol. User can use 148.5MHz for the reference clock with reference clock multiplier 20x. The source may be either external (dedicated refclk pins) or internal (FPGA core routing clock from ...
7620 - LatticeECP5/TRI-RATE SDI PHY IP Core: Can the device utilize 3G-SDI?
The Lattice ECP5 cannot support SDI Rx with a pathological pattern and, therefore, is not fully SDI-compliant. We do not recommend using the SDI solution on ECP5 unless the customer only requires SDI Tx.
6946 - What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?
Description: Spec is given that 'sync_clk_i', or the 'Sync clock frequency', can support 24-200Mhz, and it is defaulted to 60Mhz, based on CSI-2/DSI D-PHY Rx IP Core IPUG 02081 document. 'syn_clk_i' does not need to synchronize with any clocks, and ...
6138 - [ECP5]Can Tri-Rate Serial Digital Interface (SDI) PHY IP also support ECP5 devices?
Solution: The Tri-Rate Serial Digital Interface (SDI) PHY IP only supports ECP3 devices.
2722 - SERDES/ECP3:Why do I receive data errors when I configure the LatticeECP3 SERDES/PCS in TX-to-RX Serial Loopback Mode?
The TX-to-RX Serial Loopback Mode is supported in the LatticeECP3 device (see "Control Setup" and "TX-to-RX Serial Loopback Mode" sections of FPGA-TN-02190). In this loopback test mode, the TX output serial data is looped back into the RX SERDES CDR. ...