6946 - What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?

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• 6519 - MIPI CSI-2 / DSI D-PHY Receiver: What is the use of the RX_FIFO in the MIPI D-phy RX IP?

  Description: RX_FIFO is used when clk_byte_fr_i and clk_byte_o does not have the same frequency and/or is not synchronous, therefore it is used in order for the clocks to be synchronized and run at the same frequency. Nowfor the FIFO we introduce the ...

• 5923 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Can the DSI to CMOS IP be changed to DPHY1 from DPHY0?

  The user can change the hardened D-PHY blocks location between DPHY0 and DPHY1 by adding a LOCATE preference in the .lpf file to SITE "MIPIDPHY0" or SITE "MIPIDPHY1". The LOCATE preference is the following, for example: LOCATE COMP " ...

• 7265 - MIPI CSI-2 / DSI D-PHY Transmitter: What is 'Counter Width' parameter in rx_dphy IP and how to calculate the value?

  Details: 'Counter Width' refers to bus width of the counter that tracks the number of rows written during the high-speed data transition. Setting the value for Counter Width is valid only when RX_FIO type is set to 'QUEUE' where high-speed data is ...

• 7601 - Crosslink & MIPI D-PHY: How do I deal when I update the MIPI virtual channel aggregation with the latest version, I got an issue with my hardware where I cannot get an image in the stream?

  Solution: Please use the old version IP. We have tested it with the following IPs: RX v1.3 and TX v1.2. The design seems functional based on the first tests. At the time it was developed sometime in 2019, using Hard D-PHY RX might cause simulation ...

• 6512 - [MIPI CSI-2/ DSI D-PHY RX]Could you tell me about method to calculate of MIPI Rx IP's FIFO depth?

  Solution: There is no specific formula being followed in setting up the packet delay and fifo depth. What is advised is to apply similar concept to rate, time, and distance. Where the goal is to make READ and WRITE run at same speed, or atleast Write ...