7601 - Crosslink & MIPI D-PHY:
How do I deal when I update the MIPI virtual channel aggregation with the latest version, I got an issue with my hardware where I cannot get an image in the stream?
Solution:
Please use the old version IP. We have tested it with the following IPs: RX v1.3 and TX v1.2. The design seems functional based on the first tests.
At the time it was developed sometime in 2019, using Hard D-PHY RX might cause simulation issues. The latest version seems to be good for Hard D-PHY but our factory had not updated the reference design.
Since the reference design had been working on the old IP RX v1.3 and TX v1.2, we would recommend using default version as it functional and tested in hardware.
Related Articles
6114 - Crosslink NX : Are there any Reference Designs of DPHY for different applications as stated below? 1. Connecting Soft DPHY Rx module output to Soft DPHY Tx module input. 2. Image acquisition from a camera through Hard DPHY.
Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...
6504 - Crosslink-NX: How can I achieve 2.5Gbps per line for D-Phy TX?
Description: Crosslink-NX can supports 2.5Gbps per line, but when I started D-Phy TX version 1.70, the TX Line Rate per line is 160~1500 Mbps. Solution: In order for the 2.5 Gbps per lane to be supported, you need to change from Gear 8 to Gear 16. ...
5578 - CrossLink: Can Hard D-PHY blocks be configured for more than 4 lanes?
Description: This FAQ explains why Hard D-PHY blocks cannot be configured for more than 4 lanes in CrossLink product. Solution: In CrossLink product, there are 2x 4-lane D-PHY. Each of the 4-lane D-PHY runs on its own clock and has its own clock ...
6946 - What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?
Description: Spec is given that 'sync_clk_i', or the 'Sync clock frequency', can support 24-200Mhz, and it is defaulted to 60Mhz, based on CSI-2/DSI D-PHY Rx IP Core IPUG 02081 document. 'syn_clk_i' does not need to synchronize with any clocks, and ...
6067 - [CrossLink-NX] MIPI: Why does MIPI CSI-2/DSI DPHY Transmitter IP working on Radiant 2.0 but not on latest version?
If Crosslink-NX device is an ES part, it is only supported by Lattice Radiant 2.0 SP1 Software.