6504 - Crosslink-NX: How can I achieve 2.5Gbps per line for D-Phy TX?

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• 5578 - CrossLink: Can Hard D-PHY blocks be configured for more than 4 lanes?

  Description: This FAQ explains why Hard D-PHY blocks cannot be configured for more than 4 lanes in CrossLink product. Solution: In CrossLink product, there are 2x 4-lane D-PHY. Each of the 4-lane D-PHY runs on its own clock and has its own clock ...

• 6516 - CrossLink-NX / MIPI CSI-2/ DSI D-PHY:What are the Max line Rate (Mbps) of Soft Dphy for Each Package for -9 Speed Grade?

  Definition:LIFCL17 72 WLCSP: N/A (No -9 Speed Grade) LIFCL17 72 QFN: 1250 Mbps LIFCL17 121 CSFBGA: 1500 Mbps LIFCL17 256 CABGA: 1500 Mbps LIFCL40 72 QFN: 1250 Mbps LIFCL40 121 CSFBGA: 1500 Mbps LIFCL40 256 CABGA: 1500 Mbps LIFCL40 289 CSBGA: 1500 ...

• 7601 - Crosslink & MIPI D-PHY: How do I deal when I update the MIPI virtual channel aggregation with the latest version, I got an issue with my hardware where I cannot get an image in the stream?

  Solution: Please use the old version IP. We have tested it with the following IPs: RX v1.3 and TX v1.2. The design seems functional based on the first tests. At the time it was developed sometime in 2019, using Hard D-PHY RX might cause simulation ...

• 6946 - What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?

  Description: Spec is given that 'sync_clk_i', or the 'Sync clock frequency', can support 24-200Mhz, and it is defaulted to 60Mhz, based on CSI-2/DSI D-PHY Rx IP Core IPUG 02081 document. 'syn_clk_i' does not need to synchronize with any clocks, and ...

• 5389 - CrossLink: Why does the generated VHDL code does not contain any ports for CSI2/DSI D-Phy Receiver IP?

  Description: CSI2/DSI D-Phy is a submodule IP. This only provides an instantiation templates for vhdl because it is expected that it will be used in a larger design. In addition, generating this IP is done in Verilog.