7265 - MIPI CSI-2 / DSI D-PHY Transmitter: What is 'Counter Width' parameter in rx_dphy IP and how to calculate the value?
Details:
'Counter Width' refers to bus width of the counter that tracks the number of rows written during the high-speed data transition.
Setting the value for Counter Width is valid only when RX_FIO type is set to 'QUEUE' where high-speed data is buffered completely.
This setting is as described in CSI2-DSI DPHY Rx IP User Guide (FPGA-IPUG-02081):
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