7265 - MIPI CSI-2 / DSI D-PHY Transmitter: What is 'Counter Width' parameter in rx_dphy IP and how to calculate the value?

Details:

'Counter Width' refers to bus width of the counter that tracks the number of rows written during the high-speed data transition.

Setting the value for Counter Width is valid only when RX_FIO type is set to 'QUEUE' where high-speed data is buffered completely.

This setting is as described in CSI2-DSI DPHY Rx IP User Guide (FPGA-IPUG-02081):

The range of this counter is dependent on the Depth selected.

For example, 4096 depth will generate a Counter Width of 12 range.

Counter Width must be able to accommodate the maximum length of high-speed transaction including HS-Zero and trail. Each write to FIFO is DPHY Lanes x Gear Wide.

 

Another example of calculating Counter Width is as followed:

- DPHY Lanes = 4

- RX Gear = 8

- Sample word count = 3000

 

Each write to FIFO is 4 x 8 = 32 bits (4 bytes)

Requirement for HS transaction = 3000 word / 4 bytes = 750 write

 

Since 2^9 = 512 and 2^10 = 1024, 

'Counter width' must be at least 10-bit wide to accommodate this 750 write requirement.

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