Yes, our ECP5 supporst SSC. Please refer to TN1261(ECP5 and ECP5-5G SERDES/PCS Usage Guide) for the details on the section as: Spread Spectrum Clocking (SSC) Support
If the user is using a Lattice DDR3 memory controller IP core version 1.2 or later, the user can use a different rate of input reference clock. The original clock synchronization module (CSM) in the earlier version DDR3 IP cores require the fixed ...
When implementing generic DDR interface, it is required that user generate the interface using IPexpress. If not using IPexpress, the user may not implement the DELAYB element to pass the input data through to the IDDRX module. On the LatticeECP2M ...