6923 - PCIe for Nexus FPGAs: Which TLP types from the provided table are not supported by the macro/IP?
All is supported except for the locked requests.
Related Articles
PCIe DMA in Ring Buffer Operation mode unable to be stopped
Title: PCIe DMA in Ring Buffer Operation Mode Cannot Be Stopped Unexpectedly Issue Description: When the PCIe DMA is configured to operate in Ring Buffer DMA mode for continuous transfers, the DMA operation cannot be stopped unexpectedly. If a device ...6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?
Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo. Figure 1: ...7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?
Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?
Description: There are some parameters that cannot be configured using LMMI. Example, in these 2 parameters: a) Target Link Speed – this is possible. The LMMI write needs to happen before PHY out of reset b) Use TLP Interface – this is not possible ...6250 - PCIe for Nexus FPGAs: In PCIe X4 IP Core, I have selected AHB_LITE as the Data Interface Type. What is the clock domain for this interface?
clk_usr_o originates from the PCIe Core, bypassing the PCIe Soft IP. It serves as an output to an external pin. Additionally, there are two input clocks for the Soft IP: clk_usr_i at 250 MHz and clk_usr_div2_i at 125 MHz.