Clocking Network
7767 - What is the difference between PCLKT and PLLT as dedicated PLL reference clock?
Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...
7721 - All Nexus: Why does the PLL output clock period not accurately show on the simulation?
To avoid any simulation inaccuracy, use a simulation resolution limit of "10fs" or "100fs". This is a simulation limitation when using "1ps" that would lead to an offset on the clock output period. This is not applicable if the VCO period is ...
7561 - MACHXO3D: Why OSCH internal oscillator module fails to synthesize in MachXO3D devices?
Description: The OSCH module is not applicable for MachXO3D devices. MachXO3D has its internal oscillator (called OSCJ) that can be used as a clock source in a design. Please use the OSCJ internal oscillator for MachXO3D devices. Diamond's Help page ...
7176 - The input signals CLKP and CLKN are not differential!
The simulation will continue to run, but this may not reflect the actual circuit operation.
Please check the CLKP and CLKN inputs, and rerun the simulation if necessary.
Description: User will encounter the error messages during simulation using VCS tool. This is a typical response message from VCS simulator when a pair of differential clocks is fed to a DUT in a testbench. For example, the message will be seen when ...
5590 - Clock: How to route internal oscillator clock to the primary clock network in Radiant?
Description: This FAQ provide the guide to router internal oscillator clock to the primary clock network in Radiant. Solution: The “USE PRIMARY" option in Radiant Device Constraint Editor can be used to force-connect non-direct access ports to a ...
151 - Do the oscillator or timer outputs consume macrocell logic in the ispMACH4000ZE devices?
No. These blocks are built into the device using dedicated circuitry. Although these outputs can be connected to the rest of the CPLD resources as desired, no macrocell or product terms are used directly by them.
2402 - [LatticeECP3]: What is the PLL Delay Multiplier "Dynamic Mode" and why is a "Programmable Delay Unit" a range in the datasheet ?
The delay multiplier is a static value for modifying the PLL output clock's duty cycle. The delay multiplier pushes the clock edge by the equation "delay * delay multiplier". The value of a single delay block is in the datasheet page 3-34, sysCLOCK ...
1889 - MachXO2: I want to use the output of one Lattice MachXO2 I/O bank to control power on the board to the remaining VCCIO banks. Is this possible assuming that I will first power up the MachXO2 using only the VCC core and one
The user can power up the Lattice MachXO2 part using only the VCC core and one VCCIO bank. There are, however, a few constraints: As per the "Typical I/O Behavior During Power-up" section of the MachXO2 Family Data Sheet, the user needs to pick ...
1882 - PLL: When the input clock to the LatticeFPGA PLL is a Spread Spectrum Clock (SSC), does the SSC pass through the PLL, or is it filtered by the PLL?
The PLL passes the SSC input to the output because the SSC modulation frequency is far below the PLL’s bandwidth (2-4 MHz). This answer specifically applies to industrial standard Spread Spectrum Clocking with a modulation rate between 30 kHz and 33 ...
2390 - LatticeECP3: Can all Tx PLL clocks of SERDES drive the primary clock routing directly?
Description: No, only the Tx PLL half/full rate clocks in channel 0 of each SERDES quad may drive the primary clock routing directly. Eight primary clocks(CLK0~CLK7) may be used for LatticeECP3 devices. To drive the primary clock routing directly: ...
2381 - LatticeECP3: How do I implement an external reference clock for SERDES?
Description: The sources of external reference clocks for SERDES can be: Primary Clock pad (PCLK) FPGA PLL Since the extra jitter caused by the FPGA resources to route the clock to the SERDES will be passed onto the transmit data, care must be taken ...
2253 - LatticeECP3: I have a DCS feeding a PLL and when it switches in simulation my PLL loses lock.
The PLL simulation model will lose lock when there is a difference between the input and the feedback clocks. This is due to the difficulty in modelling the actual PLL hardware. TN1178 recommends that you do not switch the input clock to the PLL as ...
2251 - LatticeECP3: Why only 7 out of 8 Secondary clocks can be assigned in a clock region for LatticeECP3 devices?
In an LatticeECP3 family of devices, only 7 out of 8 SECONDARY clocks are available. One of the SECONDARY clocks does not go to the clock input of registers in the fabric. It only goes to clock enable or set/reset pins. So, the SECONDARY clocks are ...
2233 - LatticeECP3: How to avoid a DQ output from becoming a PLL input when moving from a lower to a higher density device?
The solution depends on whether or not the PCB has already been laid and the board's back is ready for use. In the schematic phase of the design, the solution is to move the DQ signal at pin T3 to another pin that is in the same DQ group that has DQ ...
896 - LatticeXP2: How to access LatticeXP2 User Electronic Signature (UES)?
LatticeXP2 UES is accessible over with JTAG port. Alternately, similar operation can be done with LatticeXP2 TAG memory access as described in the LatticeXP2 Memory Usage Guide: FPGA-UG-02080 on section 4.9 - User TAG Memory. The TAG memory is an ...
5276 - CrossLink: What is the purpose of reset_n_i signal? Is there any input timing requirement for it?
In CrossLink IPs, reset_n_i is the asynchronous reset which is used in the design to reset the state machine, flipflops, logics to the initial state. There is no specific timing requirement because it is asynchronous reset so you can reset at any ...
872 - What is the rule of thumb to assign primary clock, secondary clock, or edge clock?
For fast clocks that need to cover the majority of the FPGA with low skew between registers, use primary clock routing. The trade off when using primary clock routing is that there will be additional injection delay to route into the primary clock ...
1719 - LatticeECP3: How do I get the Lattice FPGA DCS to switch from an inactive clock to an active one in simulation?
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled. When selection input is ...
3017 - Why cannot I pack two registers with the same clock/clock enable/reset signals into one slice after MAP?
Based on Lattice FPGA architecture, two flip flops in a slice share the same clock/clock enable/reset signals. So the two registers can be packed into one slice if their control signals are same. But sometimes if the reset and/or clock enable signals ...
7140 - MachXO5: Does the FLASH_CLK_FREQ value the variation/tolerance is still ±15%?
The clock source is from our internal OSC; therefore, the variation should be the same across all FLASH_CLK_FREQ ranges.
7139 - All Nexus: Can user drive PLL dedicated clock input complement pin (GPLL_C) as the single-ended reference clock for the PLL?
For single-ended clock input to the PLL, user must use the PLL dedicated clock input true pins (GPLL_T). This is similar to the limitation with PCLK_T pins for clock pins. Complement pins must only be used for differential signaling.
804 - Power Manager II: How to read the value of NODES in the PAC-POWR1220AT8 via I2C?
The NODES in PAC-Designer for the PAC-POWR1220AT8 does not have any I2C registers associated with them. For this reason, they cannot be read directly via the I2C interface. If the NODE is routed to an actual output (HVOUT1-4 or OUT5-20) then the ...
6844 - CrossLink-NX ECLK: How can I fit 10 ECLKs on one FPGA?
For each bank, only 4 ECLKs (4 sets of PCLK pins) are available. You may be using more than 4 ECLKs per bank. Carefully, distribute and assign ECLKs to banks 3, 4, and 5 to avoid this issue. You can do this by simply assigning the clock lanes of each ...
5986 - Platform Manager II: Why is the RC filter value of LPTM21L EVB different from the recommended value of the Hardware checklist?
Description: This FAQ explains the difference of RC filter value of LPTM21L EVB and the hardware checklist. Solution: Platform Manager II, LPTM21L operates as both an I2C transmitter (in CC mode) and receiver (in HE mode). While the I2C specification ...
5974 - Platform Manager 2: How to manage the rising time of GPIO port of LPTM21L?
For the rise ramp rate of GPIO standard, it can be found in the LPTM21L IBIS file. Inside the LPTM21 ibis file: [Ramp] variable typ min max dV/dt_r 1.94/2.88n 1.72/3.31n 2.14/2.38n dV/dt_f 1.97/190.62p 1.78/364.06p 2.15/108.23p R_load = 2.50k For ...
7331 - Diamond/Radiant: How to disable GSR in Lattice Diamond/Radiant?
To fully disable GSR in Lattice Diamond and Radiant: 1. Project=>Active Strategy=>Synplify Pro settings/LSE Settings(depending on the synthesizer you are using):
6817 - IO for ECP5/ECP5-5G
ECP5 can utilize any GPIO as reset on their design, In order to utilize a dedicated routing for the reset, users may use the GSR (Global Set/Reset IO) resource. The primitive can be utilized either through inference or design instantiation. If it is ...
1687 - When implementing PCIe designs with Lattice devices that support SERDES, what should be done with the unused channels?
Single lane PCIe interfaces to root-complex carriers are often created with optional 4-lane PCIe capabilities in mind. Although this provides future capabilities of the system. it can also create unwanted issues. Connecting of the other 3-lanes (as ...
5951 - iCE40UP: If an external clock/oscillator is going to be used, what pins should be used if the intention is to utilize the primary clock routing?
Description: GBIN (Global Buffer Input) pins represent the best pin to drive a global buffer from an external source. Solution: For example, in an iCE40 Ultraplus SG48 package, the pins that can be used are Pin20, Pin35, Pin37, and Pin44. After ...
2111 - How can to select between 2 different clocks and avoid gating it using fabric resources?
FPGA devices has a Digital Clock Select (DCS) primitive/component. These primitives/components allow the user to do clock selection without leaving primary clock routing. For more information, in each architecture, please refer to sysCLOCK technical ...
2110 - LatticeECP3: How to fix netsanitycheck error when dynamic clock selector drives DDR (Double Data Rate) primitive components?
LatticeECP3 device requires dedicated or primary clock resources to drive DDR (Double Data Rate) primitive components. The clock nets from the clock input pads to the destination DDR component must use pure primary or dedicated clock nets. If you ...
6738 - All Nexus: What is the function of the PCLKDIVTESTINPX pins of the PCLKDIV primitive and what values should these pins be driven?
The PCLKDIVTESTINPX pins, together with the TESTEN_PCLKDIV and TESTMODE_PCLKDIV on the parameter lists, are signals and parameters used for test modes to test the PCLKDIV primitive in the factory. To enable normal operation, you need to set the ...
7055 - All Nexus: What pins are preferred for output clocks?
For input clocks, we can only used dedicated clock pins, PCLK or GPLL input pins for PLL reference clock. For output clocks, any IO pin can be used. There is no restriction for this.
6711 - Lattice ECP5: What is the minimum pulse width on DIRECTION, LOADN and MOVE?
The minimum width check for LOADN/MOVE/DIRECTION signal is 2500 ps. The delay setting is effective only after min time of 810 ps after the falling edge of MOVE signal.
1649 - LatticeECP2/M: Should the LatticeECP2/M SERDES PLL band be manually set to band 2 for PCI Express application?
It is better to limit the PLL band searching range and enable auto band searching to account for extreme process variations. If you use ispLEVER 8.1 Service Pack 1 or earlier software, you can add the following into your PCS config text file to limit ...
5909 - Sii9777/Sii9777: What's the latest Sii9777/Sii9777s firmware?
As of June 2021, the latest firmware versions for Sii9777/Sii9777s are as below: Receiver/Repeater(rx/rptr): 1.00.23 (released in Jun, 2020) Transmitter(tx): 1.00.14 (released in Jun, 2020)
6225 - Crosslink : Can VCCAUX operate at 1.8V?
Solution: Referring to table 4.2, Recommended Operating Conditions, when VCCAUX operate at 1.8V is below the minimum Recommended Operating Conditions. There is no guarantee the device will operate correctly. Please always ensure the power rail ...
2657 - ECP3: Why do I get a netsanitycheck Place and Route (PAR) error when a MUX drives the clock of a IDDR/ODDR component?
Description: The netsanitycheck error indicates general routing is used to drive the IDDR and/or ODDR components. The logic must be modified to use dedicated clock resources: Solution 1: Do not use generic logic (e.g. MUX implemented by LUTs) to ...
440 - Why is hotsocketing leakage current (IDK) listed separately from other IO leakage currents in Lattice data sheets?
Semiconductor devices exhibit leakage current at various conditions. For Lattice devices, we specify input/pullup/bus hold leakage current as part of the normal operational conditions. The hotsocketing leakage current (IDK) is the leakage current ...
6611 - MachXO3D: Does the NPROGCYC values in Table 3.6 of the MachXO3D datasheet applicable for all temperature grades?
Table 3.6. Programming/Erase Specifications in FPGA-DS-02026-1-7-MachXO3D-Family-Data-Sheet shows the Flash Programming cycles per tRETENTION and Flash Write/Erase cycles value for all temperature grades (Automotive, Commercial, and Industrial).
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