1649 - LatticeECP2/M:&nbsp; Should the LatticeECP2/M SERDES PLL band be manually set to band 2 for PCI Express application?<br>

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• 1965 - LatticeECP2/M:&nbsp; What do users need to consider when using the LatticeECP2/M Dynamic Clock Select (DCS)?<br>

  Documentation on LatticeECP2/M's DCS is located in page 10-29 of the LatticeECP2/M SysClock PLL/DLL Design and Usage Guide. The link to the Application note(TN1103) can be located here. One of the issues that users will run into when using the DCS is ...

• 2390 - LatticeECP3: Can all Tx PLL clocks of SERDES drive the primary clock routing directly?<br>

  Description: No, only the Tx PLL half/full rate clocks in channel 0 of each SERDES quad may drive the primary clock routing directly. Eight primary clocks(CLK0~CLK7) may be used for LatticeECP3 devices. To drive the primary clock routing directly: ...

• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...

• 1758 - MachXO2: Can the MachXO2 device support PCI-compliant signaling on any GPIO?<br>

  Yes. However, there are considerations to keep in mind when choosing pins. The MachXO2 implements two aspects of PCI buffers independently: PCI-level compliant inputs/outputs PCI complaint internal clamps. MachXO2 implements PCI-level compliant ...

• 1012 - Will all speed grades of the LatticeECP2/M and LatticeECP3 support the SerDes at 3.125 Gbps?<br>

  Yes, the SerDes/PCS is an embedded block and the performance is independent of speed grade. Only the FPGA core logic is affected by speed grade.