6738 - All Nexus: What is the function of the PCLKDIVTESTINPX pins of the PCLKDIV primitive and what values should these pins be driven?

• Related Articles

• 7055 - All Nexus: What pins are preferred for output clocks?

  For input clocks, we can only used dedicated clock pins, PCLK or GPLL input pins for PLL reference clock. For output clocks, any IO pin can be used. There is no restriction for this.

• 7197 - All Nexus: What is the default drive strength for I/O pins?

  Description: This article lists the default drive strength for different IO_TYPE for Nexus products. Solution: For Nexus products, these are the default drive strength set in Radiant SW according to the IO_TYPE, and they are applicable for both Wide ...

• 1563 - How can I implement the tri-status buffer driven by the output of ODDRXD1 in ECP3 ?<br>

  To implement the tri-status buffer driven by the output of ODDRXD1(the output DDR for DDR generic mode in X1 gearing), you should use OFD1S3AX(a primitive used to implement DDR and DDR2 DQ tri-state) to generate OE signal for the tri-status buffer, ...

• 2110 - LatticeECP3: How to fix <i>netsanitycheck </i>error when dynamic clock selector drives DDR (Double Data Rate) primitive components?<br>

  LatticeECP3 device requires dedicated or primary clock resources to drive DDR (Double Data Rate) primitive components. The clock nets from the clock input pads to the destination DDR component must use pure primary or dedicated clock nets. If you ...

• 5846 - All Devices: Can Lattice FPGA IO pins be left Floating?

  Floating IO pin is not recommended. If IO pins are left floating, then the input transistors might fall outside of the saturation or cut-off region. As a result, the device could draw additional current and increase the device's power consumption. If ...