2233 - LatticeECP3:  How to avoid a DQ output from becoming a PLL input when moving from a lower to a higher density device?

• Related Articles

• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...

• 3699 - iCE40LP: What is the output impedance of HCIOT_2 on the iCE40 LP1K device?

  Description: Refer to the Input/Output Buffer Information Specification (IBIS) model for the V-I characteristics of the LVCMOS I/O pin on the iCE40 device. The lvc330IO model has the V-I curve values for different voltages, and you can use these ...

• 1882 - PLL: When the input clock to the LatticeFPGA PLL is a Spread Spectrum Clock (SSC), does the SSC pass through the PLL, or is it filtered by the PLL?

  The PLL passes the SSC input to the output because the SSC modulation frequency is far below the PLL’s bandwidth (2-4 MHz). This answer specifically applies to industrial standard Spread Spectrum Clocking with a modulation rate between 30 kHz and 33 ...

• 880 - The LatticeXP2 device does not have a sub-LVDS output type, can I still drive sub-LVDS inputs with the LatticeXP2? <BR>

  Situation: An application uses the LatticeXP2 device and needs the sub-LVDS output type. Solution: Given that sub-LVDS signaling requires Vod from 100mv (min) to 200mv (max) and Vcm from +0.75v (min) to +1.05v (max), the sub-LVDS output type can be ...

• 6161 - iCE40 UltraPlus: How utilize Differential Input pairs on an iCE40 device?

  For iCEcube2 compatible devices (LP/HX/LM/Ultra/UltraLite/UltraPlus), the user needs to use the SB_IO primitive and override the IO_STANDARD parameter to SB_LVDS_INPUT as shown in the rudimentary example below: SB_IO SB_IO_inst ( ...