1882 - PLL: When the input clock to the LatticeFPGA PLL is a Spread Spectrum Clock (SSC), does the SSC pass through the PLL, or is it filtered by the PLL?

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• 543 - Do Lattice FPGAs support Spread-Spectrum Clocking (SSC)?

  There are two aspects to SSC support: SSC generation and SSC reception. Only the LatticeSC family provides SSC generation support. Refer to TN1099, "LatticeSC sysCLOCK PLL/DLL User’s Guide" for more information (search for "spread spectrum"). ...

• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...

• 7139 - All Nexus: Can user drive PLL dedicated clock input complement pin (GPLL_C) as the single-ended reference clock for the PLL?

  For single-ended clock input to the PLL, user must use the PLL dedicated clock input true pins (GPLL_T). This is similar to the limitation with PCLK_T pins for clock pins. Complement pins must only be used for differential signaling.

• 2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?

  Lattice recommends always using Primary Clock (PCLK) inputs for clocks. An exception is when a clock input is routed directly to a single PLL then a dedicated PLL input should be used. If multiple PLLs are using the same input clock then a PCLK Input ...

• 2253 - LatticeECP3:&nbsp; I have a DCS feeding a PLL and when it switches in simulation my PLL loses lock.<br>

  The PLL simulation model will lose lock when there is a difference between the input and the feedback clocks. This is due to the difficulty in modelling the actual PLL hardware. TN1178 recommends that you do not switch the input clock to the PLL as ...