872 - What is the rule of thumb to assign primary clock, secondary clock, or edge clock?

872 - What is the rule of thumb to assign primary clock, secondary clock, or edge clock?

For fast clocks that need to cover the majority of the FPGA with low skew between registers, use primary clock routing. The trade off when using primary clock routing is that there will be additional injection delay to route into the primary clock resources at the center of the die.

For local registers requiring low skew, a secondary clock will tend to work best and can have lower injection delay than a primary
clock.

For IOs at the edge of the device needing low skew between registers, the edge clocks will work best.

For more information, please refer to desired Lattice device family datasheets sysCLOCK section.