Yes, can do this for the for the LatticeECP2/M, LatticeECP3, and LatticeSC/M FPGA devices.
If you have a Primary clock signal that you also want to use to drive an edge clock, use the "PRIMARY2EDGE" preference. This will insure that the software routes the signals as you have intended. Otherwise the edge clock signal may take precedence and the software will use local routing resources to reach the remaining logic rather than Primary clock routing. This preference was introduced in ispLEVER version 7.1 for the LatticeECP2/M and LatticeECP3 FPGA families and is also available for the LatticeSC FPGA family.
When using the LatticeECP2/M and LatticeECP3 FPGA devices, the correct syntax for this preference with a signal named clk_400_pll is shown below:
USE PRIMARY NET "clk_400_pll" ;
USE PRIMARY2EDGE NET "clk_400_pll";
When using the LatticeSC/M FPGA devices, the correct syntax for this preference with a signal named clk_400_pll is shown below:
USE PRIMARY2EDGE NET "clk_400_pll";
You should enter this preference into the *.lpf file using the Edit Preferences (ASCII) option in Project Navigator under the Processes for current source when using ispLEVER. When using the Diamond software, open the *.lpf file by double clicking on the file name in the File List.