1151 - <p>What is the best way to divide a clock by 2 in Lattice devices?</p>
There are several different ways you could divide an incoming clock signal by 2.
You could use the internal clock divider that is provided in the LatticeECP2/M, LatticeXP2, and LatticeSC/M FPGA devices. The LatticeECP2/M and LatticeXP2 each have 2 internal clock dividers (total), while the LatticeSC/M has four internal clock dividers for each set of edge clocks. These internal clock dividers are intended for use with high speed edge clocks, so you may be better off to use internal logic for the low frequency clock signal you are using.
If you are using an older Lattice FPGA product or a Lattice CPLD product, you will need to use internal logic to create the divided clock signal.
Two methods to create a divided clock signal using internal logic are listed below:
- You could create an internal counter and use one of the counter outputs
as a divided clock signal. This is good for creating multiple divided
clock outputs. Please see the examples folder under your ispLEVER
installation folder for Verilog and VHDL examples of creating a counter.
- You could create an internal clock signal that is half the input clock signal by using the following Verilog code example. The signal "clock2" will be at half the frequency of the input clock signal labeled "clk".
always @(posedge clk or posedge rst)
beginif (rst)clock2 = 1'b0;
elseclock2 = ~clock2 ;
end
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