2116 - Lattice ECP3: The availability and cost of a 1.5V clock driver make it an unattractive solution for driving the reference clock input of the DDR3 memory interface, are there any alternatives?

Several alternatives can be used to drive the LatticeECP3 DDR3 reference clock input: 1. Use an LVDS clock driver and connect directly to the DDR3-dedicated PLL input pair. LVDS25 is a compatible I/O type that can be used in a 1.5V VCCIO bank. This method provides the best signal integrity result. 2. The user can internally drive the DDR3-dedicated PLL through the primary clock net. Choose an I/O bank of the device with an input level that is compatible with the clock driver. Connect the clock driver to the PCLK (primary clock) input pad (or differential pair) of that bank. While the primary clock can add some amount of clock net jitter to the PLL, this method is still an acceptable solution that can be used as a secondary option. This option is also good for the single-ended clock driver. 3. Another option is to use a resistor-divider circuit that translates the clock driver output level to a compatible level of the 1.5V VCCIO bank. This method is useful when the clock driver is single-ended.

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2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?
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2118 - Lattice ECP3: Can I connect an external Low Voltage Differential Signal 2.5V (LVDS25) clock output to a Lattice ECP3 DDR3 bank which is a 1.5V VCCIO bank?
Yes, the user can drive an external Low Voltage Differential Signal (LVDS) clock generator to an input pair of the LatticeECP3 1.5V VCCIO bank. Although the Lattice ECP3 LVDS25 is characterized in 2.5V and 3.3V, the user can safely use an external ...

2116 - Lattice ECP3: The availability and cost of a 1.5V clock driver make it an unattractive solution for driving the reference clock input of the DDR3 memory interface, are there any alternatives?

2116 - Lattice ECP3: The availability and cost of a 1.5V clock driver make it an unattractive solution for driving the reference clock input of the DDR3 memory interface, are there any alternatives?

Related Articles

6498 - XO/ECP: What is the expected GPLL input clock tR and tF requirements for XO2, XO3, ECP3 and ECP5 ?

What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

7139 - All Nexus: Can user drive PLL dedicated clock input complement pin (GPLL_C) as the single-ended reference clock for the PLL?

2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?

2118 - Lattice ECP3: Can I connect an external Low Voltage Differential Signal 2.5V (LVDS25) clock output to a Lattice ECP3 DDR3 bank which is a 1.5V VCCIO bank?