6498 - XO/ECP: What is the expected GPLL input clock tR and tF requirements for XO2, XO3, ECP3 and ECP5 ?

• Related Articles

• 7139 - All Nexus: Can user drive PLL dedicated clock input complement pin (GPLL_C) as the single-ended reference clock for the PLL?

  For single-ended clock input to the PLL, user must use the PLL dedicated clock input true pins (GPLL_T). This is similar to the limitation with PCLK_T pins for clock pins. Complement pins must only be used for differential signaling.

• 1946 - [LatticeECP3/LatticeECP2/MachXO2/XP2] Are there hardware resources that helps me to achieve my input HOLD requirements?

  Yes, there are such resources in select Lattice devices. There are three different resources that you can use to do this. They are: 1). FIXEDDELAY: Supported in ECP3, MachXO2, and XP2 devices. 2). DELAYC: Supported in ECP3 devices. 3). DELAYB: ...

• 2116 - Lattice ECP3: The availability and cost of a 1.5V clock driver make it an unattractive solution for driving the reference clock input of the DDR3 memory interface, are there any alternatives?

  Several alternatives can be used to drive the LatticeECP3 DDR3 reference clock input: 1. Use an LVDS clock driver and connect directly to the DDR3-dedicated PLL input pair. LVDS25 is a compatible I/O type that can be used in a 1.5V VCCIO bank. This ...

• 2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?

  Lattice recommends always using Primary Clock (PCLK) inputs for clocks. An exception is when a clock input is routed directly to a single PLL then a dedicated PLL input should be used. If multiple PLLs are using the same input clock then a PCLK Input ...

• 6161 - iCE40 UltraPlus: How utilize Differential Input pairs on an iCE40 device?

  For iCEcube2 compatible devices (LP/HX/LM/Ultra/UltraLite/UltraPlus), the user needs to use the SB_IO primitive and override the IO_STANDARD parameter to SB_LVDS_INPUT as shown in the rudimentary example below: SB_IO SB_IO_inst ( ...